The present invention generally relates to memory devices. More specifically, the present invention relates to memory devices with divided bit-line, shared sense amplifier architecture.
FIG. 1 is a simplified block diagram of a conventional dynamic random access memory or DRAM showing an illustrative structure of a memory cell array 10. The memory cell array 10 is made up of many unit memory cells, each of which is usually individually addressable and used to store a bit. The unit memory cell has a capacitor which holds the data in the form of electrical charges, and an access transistor which serves as a switch for selecting the capacitor. Unit memory cells are located at the intersection of word lines WLx (or rows) and bit lines BLx (or columns). The access transistor""s gate is connected to the word line WLx. The source of the access transistors are connected to the bit lines BLx. Each pair of complementary bit lines is connected to a sense amplifier 12.
Memory access begins when a word line is selected (via the decoding of a row address) thereby switching on all the access transistors connected to that word line. In other words, all the unit memory cells in that particular row are turned on. As a result, charge in the capacitor within each unit memory cell is transferred onto its corresponding bit line causing a charge imbalance which leads to a potential difference between the pair of complementary bit lines. This potential difference is detected and amplified by a sense amplifier 12. This amplified potential difference is then transferred to the I/O gate activated based on the column address, which in turn transfers the amplified signal to the data output buffer.
Furthermore, the precharge/equilibration circuit 14 plays a significant role in detecting memory data during the course of a memory access operation. In advance of a memory access and the activation of a word line, the equilibration circuit 14 charges all bit line pairs up to a certain potential which usually equals to half of the supply potential, that is, Vdd/2. As shown in, for example, FIG. 1, the bit line pairs are short-circuited by a transistor so that they are each at an equal potential. The precharging and potential equalization by the equilibration circuit 14 is important due to the disparate difference in capacitance between the bit lines and the storage capacitor. Since the capacitance of the storage capacitor is far less than that of the bit lines, when the storage capacitor is connected to the bit lines via the access transistor, the potential of the bit line changes only slightly, typically by 100 mV. If the storage capacitor was empty, then the potential of the bit line slightly decreases; if charged, then the potential increases. The activated sense amplifier amplifies the potential difference on the two bit lines of the pair. In the first case, it draws the potential of the bit line connected to the storage capacitor down to ground and raises the potential of the other bit line up to Vdd. In the second case, the bit line connected to the storage capacitor is raised to Vdd and the other bit line decreased to ground.
Each bit line BLx can be viewed as a column. The width between a pair of complementary bit lines, e.g., BLx and its complement {overscore (BL)}x, is commonly known as the bit-line pitch or two-column pitch. As can be seen from FIG. 1, the physical width of each sense amplifier 12 is roughly the same as the two-column pitch, i.e., the width between the pair of complementary bit lines. With the rapid development of semiconductor fabrication techniques, the unit memory cell and thus the two-column pitch is increasingly becoming smaller and smaller. Consequently, with the smaller dimensions, the density of bit lines within the same unit area is also increased. This increase in bit-line density, however, cannot be fully exploited if the size and physical shape of the sense amplifiers 12 remains the same. As FIG. 1 shows, since the sense amplifiers 12 are lined up in a row, the size of the sense amplifiers 12 has to correspondingly decrease to realize the full benefit of the narrower two-column pitch. Therefore, it would be desirable to provide a method and apparatus for reducing the size of sense amplifiers so as to take advantage of the narrower two-column pitch of complementary pairs of bit lines.
FIG. 2 shows half of a sense amplifier circuit commonly used in memory circuits to detect potential difference between bit line pairs. The source of the transistors N20, N30 are connected together at a predetermined bit line potential. The gate of one transistor is connected to the drain of the other transistor.
In accordance with conventional methods, as the two-column pitch between the bit line pairs becomes smaller, the sense amplifiers have to be correspondingly laid out in a long and narrow manner to match the narrower column pitch.
FIG. 3 shows a conventional fabrication layout for the sense amplifier circuit shown in FIG. 2 laid out in the longer and narrower shape to fit the smaller two-column pitch. As shown in FIG. 3, the source, drain, and gate areas of the two cross-coupled transistors N20, N30 are laid out in parallel to the bit lines. Note that in this example, first layer poly (poly 1) is used for transistor gate terminals and second layer poly (poly 2) is used for bit lines. When laid out in this manner, however, the sense amplifier makes very inefficient use of the surface area. A more compact layout, as described below, is much preferred in order to maximize the use of the surface area.
FIG. 4 shows an alternate fabrication layout for the sense amplifier circuit shown in FIG. 2 wherein the transistors are laid out at right angle to the bit lines. The right-angle configuration of FIG. 4 clearly requires less surface area than that shown in FIG. 3. For example, unlike the layout configuration of FIG. 3, this layout configuration allows the common source regions of the two transistors to be shared in one active area 16, thereby saving the area that would otherwise have been needed for an additional, physically separate source region. Further, under the right-angle configuration, the contacts 18 for the connections between the gate and the bit lines and between the drain and the bit lines can fit within the active areas, therefore, obviating the need to have additional space to accommodate the contacts. While the right-angle layout generally conserves total surface area, such layout, however, requires a wider two-column pitch as shown. It, therefore, cannot be used unless the two-column pitch requirements are relaxed.
With the use of three-layer metal in semiconductor fabrication processes, a divided bit-line, shared sense amplifier configuration is made possible. FIG. 5 shows a conventional DRAM memory circuit with a divided bit-line, shared sense amplifier architecture. The sense amplifiers are arranged in banks 20, 30 and each sense amplifier, for example, sense amplifier 30a, is shared between adjacent memory arrays 40, 50 and is connected to a pair of complementary bit lines 22, 24 from each memory array 40 or 50. A block select circuit is located on each side of a shared sense amplifier 30a. The block select circuit, which includes transistors N1, N2, N3 and N4, is controlled by block selection signals 26, 28 and is used to control the connection between the sense amplifier 30a and the pair of complementary bit lines 22, 24 from an adjacent memory array 40 or 50. The use of the block select circuits on both sides of a bank 30 of sense amplifiers allows the sense amplifiers to be shared between adjacent memory arrays 40, 50 and also ensures that only one of the two adjacent memory arrays 40, 50 can use the bank 30 of sense amplifiers on an exclusive basis at all times.
As illustrated in FIG. 5, for example, an adjacent memory array 40 is further made up of two memory sub-arrays 40a, 40b. To reduce capacitive loading of the bit lines in a given memory array 40, poly bit lines from the two memory sub-arrays 40a, 40b are not connected together. Instead, each poly bit line, for example, poly bit line 22 to be coupled to a sense amplifier 30a is generally divided into two independent segments 22a, 22b. The first segment 22a is located in the memory sub-array 40a closest to the sense amplifier 30a and is coupled to the sense amplifier 30a. The second segment 22b is located in the memory sub-array 40b farther away from the sense amplifier 30a and is coupled to a metal line 22m. The metal line 22m, in turn, is coupled to the sense amplifier 30a. As a result of the coupling between the second segment 22b and the metal line 22m, there is a bit-line metal-to-poly contact area 32 located between the two memory sub-arrays 40a, 40b. While it is preferable that the bit-line metal-to-poly contact area 32 is located generally at the midpoint of a memory array 40, such location is by no means a requirement and can be situated at any point within the boundary of the memory array 40. By coupling the second segment 22b to the metal line 22m, the capacitive loading of the second segment 22b is much reduced. The operation of this conventional DRAM memory circuit as shown in FIG. 5 is commonly understood by a person of ordinary skill in the art. Exemplary dimensions (in microns) for various circuit blocks in the device are also shown in FIG. 5. For example, each memory sub-array 40a, 40b is 200 xcexc wide separated by a 5 xcexc wide bit-line metal-to-poly contact area 32.
Moreover, under conventional bit-line designs, as shown in FIG. 1, the equilibration circuit 14 is generally located at the beginning of the bit lines. As the bit lines become longer and longer, especially in the case of a divided bit-line configuration, the time it takes to precharge an entire bit line from beginning to end proportionally increases, thereby creating unnecessary delay between memory accesses. Therefore, it would be desirable to provide a method and apparatus for optimally positioning a precharge/equilibration circuit so as to reduce the precharging time of bit lines.
Further, it would be desirable to provide a more efficient fabrication layout for the equilibration circuit 14 so as to minimize the amount of area needed to implement such circuit on a chip.
The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line configuration, segments of poly bit lines are generally coupled to metal lines via a bit-line metal-to-poly contact area to reduce capacitive loading. In one embodiment of the present invention, a number, for example, half, of the sense amplifiers from a given bank are physically relocated to the bit-line metal-to-poly contact area inside the memory array. This relocation frees up silicon area for the sense amplifiers, allowing each sense amplifier to be laid out in, for example, a right-angle configuration.
Furthermore, selected bit lines from two adjacent memory sub-arrays are coupled to metal lines within the relocated sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.
In addition, various layout structures for the equilibration circuits are presented to maximize the use of silicon area on a chip.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements and letters at the end of reference numbers are used for ease of reference to further differentiate each of a number of identical or functionally similar elements.